Subject: Re: Assigning / testing different sizes -- shouldn't we restrict the use?
From: VhdlCohen@aol.com
Date: Mon Aug 06 2001 - 14:40:00 PDT
Below is code with a 4-bit input port and a 1-bit output port.
Testing the 4-bit input against a 1-bit value or a value greater thatn
4-bits seems OK in synthesis.
Also writing a 4-bit value onto a 1-bit port seems also OK in synthesis.
What does that mean in hardware? Obvioulsy, this is an error, and similar
code would NOT compile in VHDL.
Question to this group: Shouldn't we restrict such erroneous use of Verilog
for synthesis (i.e., make it an error)?
Incidentally, code as shown below is difficult to automatically translate
into VHDL (thinking of automatic tools), and makes no hardware sense.
<<Verilog lint checkers already flag such cases. A good synthesis tool also
generates warnings for such.>>
There is NO requirement in our spec that "lint checkers must be used prior to
synthesis".
If we do that, then we have to define what a lint checker does. Also, I
tried 2 synthesis tools (Synplify and Xilinx WebPack, and both of them
accepted the verilog code with NO complaints or warnings, and wired ain[0] as
the vector.
For integers, sometimes the logic does not make sense. For example:
if (ain > 35) -- This is always false because ain max value is 15!!!
This is also the case (for integers only) in VHDL.
module testlog (ain, clk, cout/*AUTOARG*/ ) ;
input [3:0] ain;
input clk;
output cout;
reg cout;
always @ (posedge(clk)) begin
if (ain == 1'b0)
cout <= ~ain;
else if (ain > 35) -- This is always false because ain max value is 15!!!
cout <= ^ain;
else
cout <= ain;
end
endmodule
Below is a VHDL model that is equivalent to the Verilog code.
Compilation with ModelSim and ncvhdl are alos included.
Ben
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_UNSIGNED.all;
entity testlog is
port (ain : in std_logic_vector(3 downto 0); -- 4 bits
clk : in std_logic;
cout : out std_logic) ; -- 1 bit
end entity;
architecture beh of testlog is
begin
process (clk)
variable tmp : std_logic;
begin
if (clk'event and clk = '1') then
if (ain = '0') then -- if (ain == 1'b0)
cout <= not ain; -- 1bit assigned the NOT of 4 bit input vector
//ERROR
elsif (TO_INTEGER(ain) > 35) then
tmp := '0';
for i in ain'range loop
tmp := tmp xor ain(i);
cout <= tmp; -- cout <= ^ain;, -- 1 bit assigned a 1 bit OK here
end loop; -- if ain > 35
else
cout <= ain; -- cout <= ain; -- 1 bit assigned 4 bits //ERROR
end if;
end if; -- clock edge
end process;
end architecture beh;
%vcom -93 testlog.vhd
Model Technology ModelSim SE/EE vcom 5.4b Compiler 2000.06 Jun 8 2000
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Loading package numeric_unsigned
-- Compiling entity testlog
-- Compiling architecture beh of testlog
ERROR: testlog.vhd(16): No feasible entries for infix op: "="
ERROR: testlog.vhd(16): Type error resolving infix expression.
ERROR: testlog.vhd(17): Type error resolving prefix expression.
ERROR: testlog.vhd(25): Type error in variable ain. Needed type std_logic.
ERROR: testlog.vhd(29): VHDL Compiler exiting
%ncvhdl -v93 testlog.vhd
ncvhdl: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc.
if (ain = '0') then -- if (ain == 1'b0)
|
ncvhdl_p: *E,OPTYMM (testlog.vhd,16|14): operator argument type mismatch
87[4.3.3.2] 93[4.3.2.2] [7.2] [10.5].
cout <= not ain; -- 1bit assigned the NOT of 4 bit input vector
//ERROR
|
ncvhdl_p: *E,EXPTYP (testlog.vhd,17|18): expecting an expression of type
STD_ULOGIC 87[8.3] 93[8.4].
cout <= ain; -- cout <= ain; -- 1 bit assigned 4 bits //ERROR
|
ncvhdl_p: *E,EXPTYP (testlog.vhd,25|20): expecting an expression of type
STD_ULOGIC 87[8.3] 93[8.4].
%
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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