Subject: Re: Inferring FPGA Hardware Features?t
From: Joseph P. Wetstein (jpw@cbis.ece.drexel.edu)
Date: Tue Jul 17 2001 - 11:56:50 PDT
Doesn't a more general IFDEF () support this concept? Perhaps it can be
applied to the case of the attributes as well as the code...
Joe
>
> What I am describing has to do with reuse -- Imagine that at one time
> I wanted a particular transformation, or attribute to be attached to a
> particular construct. At some later time when I reuse that construct
> in a different way, I do not want the particular attribute attached
> anymore. I could certainly edit the text the second time; but that
> becomes tedious and error prone.
>
> It is the case that certain attributes will remain for all time true
> about a particular item; i.e., a case statement is parallel.
>
> Other attributes, such as 'optimize for speed', or 'use cell 56' may
> only be true for one use of the construct.
>
> What I am ruminating about is whether we need conditional attributes.
>
> wire [31:0] a (* if (PentiumIII) maxdriver=1;
> else if (PentiumIV) maxdriver=2;
> else maxdriver=10; */ ;
>
> I am not convinced that if we provided this, that as a pratical matter
> users will use it correctly; however without a method to conditionally
> turn on or off certain attributes, they become less useful than they
> could be.
>
> -mac
>
> Shalom Bresticker writes:
> > [1 <text/plain; us-ascii (7bit)>]
> > Mac,
> >
> > You're correct, but I'm not sure that is a problem.
> >
> > You say, "hence I don't get what I want".
> > Well, if that's the case, then if you're the one developing the module, then don't put it in.
> > If you're the one wanting to reuse it, then it won't fit your needs.
> >
> > On the other hand, if the alternative is having to ADD that attribute to get what you want,
> > then it's also not reusable without change.
> >
> > It simply becomes one of the characteristics of that module.
> >
> > Am I way off base here ?
> >
> > Shalom
> >
> >
> > Michael McNamara wrote:
> >
> > > My point is extremely pragmatic. If I insert into a module a pragma
> > > that states something, like (* implement this in cell 14 *), then
> > > when I instatiate this module more than once, I will have two cells
> > > that are trying to use cell 14.
> > >
> > > If I state in a module, (* optimize for time *), then _every_
> > > instatiation of that module will be requesting timing optimization;
> > > including instantiations that are not timing critical; hence I don't
> > > get what I want.
> >
> > --
> > **************************************************************************
> > Shalom Bresticker Shalom.Bresticker@motorola.com
> > Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
> > P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
> > **************************************************************************
> >
> >
> > [2 <text/html; us-ascii (7bit)>]
> >
>
-- Joseph P. Wetstein, P.E. j.wetstein@ieee.org (707) 202-0600 fax PP/ASEL & KA3VJY [Tech+]
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