Subject: RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Thu Apr 04 2002 - 12:37:11 PST
REMINDER!
-----Original Message-----
From: Jayaram Bhasker
Sent: Friday, March 29, 2002 10:54 AM
To: vlog-synth@eda.org
Subject: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr
5, '02
The next Verilog RTL Synthesis Interoperability WG meeting is scheduled as
a teleconference for Friday, April 5, 2002.
The call details are:
CALL DATE: APR-05-2002 (Friday)
CALL TIME: 12:00 PM EASTERN TIME
DURATION: 1 hr 30 min
USA Toll Free Number: 888-396-9971
USA Toll Number: +1-712-271-0003
PASSCODE: 39996
LEADER: Mr Jayaram Bhasker
Agenda:
1. IEEE standardization process update.
2. Discussion on test_port attribute.
3. Any other issues posted on review of draft 2.1.
4. This would most probably be our last regular Working Group meeting.
Regards,
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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