Subject: Re: attribute: test_port // more comments
From: VhdlCohen@aol.com
Date: Thu Apr 04 2002 - 17:54:55 PST
Daryl,
Question: How do you know where in hierachy module will be instantiated?
Lets say module A has internal wire S used as a test port.
A is instantiated in B, B in C, C in D.
A is also instantiated in E, E in F.
Now what's the name of test port for S?
My other concern though is:
Lets say module A has internal wire S used as a test port.
S has a keep and test_port attribute.
S is connect to regA, which is optimized out by synthesis tool.
S gets connect to test port, but is really internally connected to
nothing!
I guess vendors should report this as a warning.
BEN
> I agree with your comment that this is a tool issue. As such even the notes
> may be superfluous and I'm happy with your answer.
>
> I think I was wondering if there was some uniform way of making connections
> to
> test ports more explicit. If each test port could somehow be associated
> with
> its hierarchical name in the netlist, for example, then connections could
> be
> made to specific ports more easily (across all tools).
>
> Maybe it's possible to require a reg/net attributed "test_port" (or just
> "keep") to be available as an escaped identifier generated from the
> hierarchical name?
>
> eg
> (* synthesis, test_port *) reg foo;
> inside module bar would result in an escaped identifer
> \bar.foo
> representing the reg object.
>
> Or is escaped identifier not permissible in a netlist?
> Or does this step on tools' toes by over-specifying naming conventions?
>
> Users could then have
>
> `ifdef SYNTHESIS
> `define BARFOO \bar.foo
> `else
> `define BARFOO bar.foo
> `endif
>
> followed by accesses to `BARFOO in testbenches
>
> or
>
> `ifndef SYNTHESIS
> wire \bar.foo = bar.foo;
> `endif
>
> followed by accesses to \bar.foo
>
> Maybe this would be useful for keep instead, as it needs no ports?
>
>
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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