Subject: attribute: test_port // more comments
From: VhdlCohen@aol.com
Date: Fri Mar 29 2002 - 12:45:07 PST
Muzaffer Kal expressed a concern about the keep of test ports (i.e.,
optimization of objects attibuted as test ports), and the creation of
multiple copies of test ports when module is instantiated multiple times.
Actually there is an easily solution to both of these issues:
1. Use the KEEP in addition to the TEST_PORT attribute
2. Add a parameter to identify which instance you want the test port to come
out.
Below is an example (we may want to show this in our spec
module ff (q, d, clk, rst);
parameter WIDTH = 1;
parameter TEST_PORT = 1; // 1 => ON, 0 => OFF
output [WIDTH-1:0] q; // output
input [WIDTH-1:0] d; // data input
input clk; // clock
input rst; // reset, active hi
reg [WIDTH-1:0] q; // FF output
(* synthesis, keep, // Do not remove in optimization
test_port = TEST_PORT *) // bring to a test port
wire [WIDTH-1:0] qbar; // test point
assign qbar = ~q; // equation for test point
always @(posedge clk or posedge rst) begin
if (rst) q <= {WIDTH{1'b0}};
else q <= d;
end
endmodule //ff
module top (q, d, clk, rst);
parameter WIDTH = 2;
parameter WIDTH_ONE = 1;
parameter TEST_PORT_ON = 1;
parameter TEST_PORT_OFF = 0;
output [WIDTH-1:0] q; // output
input [WIDTH-1:0] d; // data input
input clk; // clock
input rst; // reset, active hi
// ff #(.WIDTH (1),
// .TEST_PORT (1))
ff #(WIDTH_ONE, TEST_PORT_ON) // bring test port out
ff_1 (
// Outputs
.q (q[0]),
// Inputs
.d (d[0]),
.clk (clk),
.rst (rst));
// ff #(.WIDTH (1),
// .TEST_PORT (0))
ff #(WIDTH_ONE, TEST_PORT_OFF) // do NOT bring test port out
ff_2 (
// Outputs
.q (q[1]),
// Inputs
.d (d[1]),
.clk (clk),
.rst (rst));
endmodule // top
I still believe that we need to do the following, as written in my previous
email:
Change from:
"In the case where the reg infers a storage device, it is the output of the
storage device that shall be used to create the test port."
TO:
Only objects that represents bits or bit vectors shall be used to create the
test port.
Rationale: It might be difficult for a tool to determine the "output of a
storage device".
ADD:
If a test ported attributed object is optimized out, that object shall not be
mapped onto a port, unless there is a "keep" attribute (see section 6.1.4 d).
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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