Subject: Re: attribute: test_port // more comments
From: VhdlCohen@aol.com
Date: Wed Apr 03 2002 - 12:31:53 PST
In a message dated 4/3/02 4:38:32 AM Pacific Standard Time,
Daryl.Stewart@cl.cam.ac.uk writes:
> The description of test_port does not explain the order in which the new
> ports
> are added, or whether they are given .-names for connection, and if so what
>
> the .-names are.
Good question, but isn't that a tool issue rather than a spec issue?
I think we could add a note that says something like:
" The name of the test port shall be determined by the synthesis tool, and is
not specificed in this document".
> ADD: >
> > If a test ported attributed object is optimized out, that object shall
> not be
> > mapped onto a port, unless there is a "keep" attribute (see section 6.1.4
> d).
>
> Assuming the optimization-out of an object may change between
> synthesis-runs, is there a way to tell when your test port disappears?
Good question, but isn't that a tool issue rather than a spec issue?
I think we could add a note that says something like:
" The appearance or omission of a test port as a result of optimization may
be reported by the synthesis tool, and is not specificed in this document".
> A pathological case is where there are two submodules:
> In my first synthesis, the first module produces a test-port, while the
> other does not, due to an optimisation.
> After changing my code, the next synthesis run optimises the first module's
> port away, but this time the second module's is not.
> Now the parent module still has a test-port added to it, but how do I know
> where it came from??
>
Again, this is a tool issue, and above note takes care of that.
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