Re: 6.1 Synthesis attributes // minor syntax update


Subject: Re: 6.1 Synthesis attributes // minor syntax update
From: VhdlCohen@aol.com
Date: Wed Apr 03 2002 - 12:20:31 PST


In a message dated 4/3/02 3:50:45 AM Pacific Standard Time,
Daryl.Stewart@cl.cam.ac.uk writes:
> (* synthesis, <attribute=value_or_optional_value>
> {, <attribute=value_or_optional_value> } *)
Yes, thanks for the correction.
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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