I have read your comments and Paul Menchini's comments concerning the use
of "meta-logical values". To my knowledge, the term meta-logical value does
not appear in the IEEE 1364 standard, probably because x and z are the only
meta-logical values that exist in Verilog.
Unless the goal is to convert the language of all Verilog standards into
VHDL-like language, I see no reason to introduce the term meta-logical
values in a Verilog-related document.
The term meta-logical probably makes sense in VHDL because of all of the
other non-logic values and enumerated types, but in Verilog, we would have
to define and then use the term everywhere else in the spec. One silly
reason not to include the term "me-ta-lo-gi-cal val-ues" is because it is
seven syllables and does not have an intuitively obvious meaning to most
non-VHDL hardware engineers. On the other hand the term, "x and z" is three
syllables, and requires no further definition to even non-HDL engineers.
In the IEEE 1364-1995 standard, page 13, the four basic values are listed,
including:
"x - represents an unknown logic value"
"z - represents a high-impedance state"
The entire 1364 standard is full of references to (also on page 13):
"When the z value ... an x value. ..." (etc.)
Verilog engineers frequently think of x and z as logical values since
Verilog has the === and !== operators which permit us to do non-case
comparisons against x and z. A nifty little way to locate suspected
unknowns on an address bus from a testbench is to code the following:
always @(addr)
if (^addr === 1'bx) $display("ERROR at time %0d: addr = %b", $time, addr);
The exclusive-or reduction captures unknowns and then permits a useful
debugging message to be printed.
I really see no reason to add meta-logical to a Verilog specification
unless you propose to similarly change the entire IEEE 1364 standard. I
would like the Verilog synthesis standard to be consistent with the Verilog
standard and not necessarily strictly consistent with the VHDL standards.
Proposed changes and typo-corrections are shown below.
Regards - Cliff Cummings
At 09:14 AM 3/10/99 -0500, you wrote:
>Oops, I forgot to add few other statements to the proposal. Here is
>an updated one.
>
>Here is an UPDATED proposal, to add to section 5, on how x and z values
are to be
>interpreted for synthesis.
>
>--------------------------
>
>5.5 Support for meta-logical values, x and z
Cliff Cummings - proposal: "5.5 Support for x and z values"
>The value x may be used only as a primary on the RHS of an assignment
>to indicate a dont care value for synthesis.
Typo: "don't care"
>The value x may be used in case item expressions in a casex statement to
>imply a dont care value for synthesis.
Typo: "don't care"
>The value x may be used in a case item expression in a case statement;
however
>such a branch is never expected to occur for synthesis.
>
>The value x shall not be used with any operators or mixed with other
expressions.
>
>The value z may be used only as a primary on the RHS of an assignment to
>infer a three-state driver as described in section 5.4.
>
>The value z (or ?) may be used in case item expressions for casex and casez
>statements to imply a dont care value for synthesis.
Typo: "don't care"
>The value z may be used in a case item expression of a case statement;
however
>such a branch is never expected to occur for synthesis.
?? - Why is this permitted? (z in a case expression?)
>The value z shall not be used with any operators or mixed with other
expresions.
Typo: "expressions"
>-------------------------
>
>Please provide your comments on this UPDATED proposal by March 15.
>
>- bhasker
>
>
>----- Begin Included Message -----
>
>>From owner-vlog-synth@eda.org Mon Mar 8 16:16 EST 1999
>X-Authentication-Warning: server.eda.org: majordom set sender to
owner-vlog-synth@eda.org using -f
>Date: Mon, 8 Mar 1999 16:12:11 -0500 (EST)
>From: Jayaram Bhasker <jbhasker>
>To: vlog-synth@eda.org
>Subject: Support for values x and z
>X-Sun-Charset: US-ASCII
>Sender: owner-vlog-synth@eda.org
>Content-Type: text
>Content-Length: 686
>
>Here is a proposal, to add to section 5, on how x and z values are to be
>interpreted for synthesis.
>
>--------------------------
>
>5.5 Support for non-logical values, x and z
>
>The value x may be used only as a primary on the RHS of an assignment
>to indicate
>a dont care value for synthesis.
>
>The value x shall not be used with any
>operators or mixed with other expressions.
>
>The value z may be used only as a primary on the RHS of an assignment to
>infer a three-state driver as described in section 5.4.
>
>The value z shall not be used with any operators or mixed with other
expresions.
>
>-------------------------
>
>Please provide your comments on this proposal by March 15.
>
>- bhasker
>
>
>----- End Included Message -----
>
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