Subject: Re: Section 7.7.9.1 - Initial Blocks - Illegal??
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Apr 11 2002 - 09:15:54 PDT
At 07:21 AM 4/11/02 -0700, you wrote:
>Cliff,
>
>How do you feel about a warning for initial blocks:
>
> module m(q, d);
> output q;
> input d;
> assign q = d;
>
> initial
> $display("hello, world");
> endmodule
>
>--> WARNING: 'initial' statement is not supported for synthesizable module
> (File test_initial.v, Line 6) <VLOGPT-035>.
A warning is certainly better than nothing but my experience has been that
most users miss or ignore warnings.
>I agree that non-synthesizable constructs should not be accepted quietly,
>but the question of whether to warn or error out depends in part on how many
>such constructs the tool is likely to see. At one time in the misty past
>the Ambit parser did error out for initial statements, but was later changed
>to accept them with a warning.
Synopsys does error out on initial blocks. I think Ambit had it right when
it flagged errors for initial blocks. I think Synplicity is doing a
horrific disservice by ignoring initial blocks in RTL code. Until recently,
Synplicity was only used for FPGAs (and it is still predominantly used for
FPGAs) so when the design screws up, the users can relatively easily fix
the problem. Now that they are entering the ASIC synthesis world, an
argument can be made that their tool could be liable for an ASIC turn and
all associated costs.
I guess I should not complain. I guess I should just offer my services as
an expert witness in trials by companies against EDA companies that let
this slip by. Ignoring initial blocks is truly a very bad idea.
(I guess I now have a topic for a future conference paper ;-)
>Paul
Regards - Cliff
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