Subject: re: Ballot feedback: test_port
From: VhdlCohen@aol.com
Date: Mon Jul 15 2002 - 16:40:32 PDT
The other issue with "test_point" is that you lose the notion that the signal
in question is brought out to a "port".
"test_port" seems to better indicate that notion of "bring that signal to a
'port' for 'test'.
I don't get this concept of "expectation that this affects post production
tests'".
Perhaps some can explain that to me. In fact, if I were to activate and keep
this attribute, no matter what its name is, I'll ave a port for test in the
final production.
My recomendation: NO CHANGE.
Ben
<One of the comments recd during ballot was to rename the "test_port"
attribute
as "probe_point". Here is the exact comment:
"test_port seems to be a misleading name for this functionality.
probe_point seems to better get to the intent of the attribute, and does not
lead to user expectation that this affects post production test."
I would like feedback from the WG on whether "probe_point" is a better name
for
the attribute or not.>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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