Subject: Re: vector bit-select in sensitivity list
From: Paul Graham (pgraham@Cadence.COM)
Date: Fri Aug 09 2002 - 07:45:20 PDT
> Yes, you should be able to say
>
> module foo (
> input [7:0] a,
> input b,
> input d,
> output reg c);
>
> however there is a bug in the 2001.08 version of PRESTO:
So presto has a bug in that it can't accept legal verilog, and the
workaround is to supply it with illegal verilog. This is how de-facto
standards get started...
Paul
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