Subject: Re: vector bit-select in sensitivity list
From: Steve Golson (sgolson@trilobyte.com)
Date: Fri Aug 09 2002 - 06:12:47 PDT
Paul Graham wrote:
>
> Your example appears to be illegal. LRM 12.3.4 seems to say that no port
> declared in a list_of_port_declarations may be redeclared in the body of the
> module. Yet in your example port 'c' is redeclared in the reg declaration.
> Am I misconstruing the LRM?
>
> > module foo (
> > input [7:0] a,
> > input b,
> > input d,
> > output c);
> >
> > reg c;
> >
> > always @ (b, a[5], d)
> > c = a[5] && b;
> >
> > endmodule
>
> Paul
Yes, you should be able to say
module foo (
input [7:0] a,
input b,
input d,
output reg c);
however there is a bug in the 2001.08 version of PRESTO:
Compiling source netlist file /home/sgolson/play/foo.v
Error: /home/sgolson/play/foo.v:5: Syntax error at or near token "reg". (VER-294)
*** Presto compilation terminated with 1 errors. ***
Error: Can't read 'verilog' file '/home/sgolson/play/foo.v'. (UID-59)
You can work around this bug by declaring the reg separately.
-seg
Steve Golson / Trilobyte Systems / +1.978.369.9669 / sgolson@trilobyte.com
Consulting in: Verilog, Synopsys, patent analysis, reverse engineering
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