Subject: Re: vector bit-select in sensitivity list
From: Shalom.Bresticker@motorola.com
Date: Fri Aug 09 2002 - 03:09:03 PDT
Paul,
I don't have the LRM with me, but what I think it says
is either that if the port declaration includes a net/var type, such as reg,
then it may not be so redeclared, or that if the port declaration includes the
type
of port (e.g., output) then it may not be so redeclared.
Does it actually say something different?
Shalom
On Thu, 8 Aug 2002, Paul Graham wrote:
> Date: Thu, 8 Aug 2002 20:13:32 -0700 (PDT)
> From: Paul Graham <pgraham@cadence.com>
> To: sgolson@trilobyte.com
> Cc: mac@verisity.com, Shalom Bresticker <Shalom.Bresticker@motorola.com>,
vlog-synth@eda.org
> Subject: Re: vector bit-select in sensitivity list
>
> Your example appears to be illegal. LRM 12.3.4 seems to say that no port
> declared in a list_of_port_declarations may be redeclared in the body of the
> module. Yet in your example port 'c' is redeclared in the reg declaration.
> Am I misconstruing the LRM?
>
> > module foo (
> > input [7:0] a,
> > input b,
> > input d,
> > output c);
> >
> > reg c;
> >
> > always @ (b, a[5], d)
> > c = a[5] && b;
> >
> > endmodule
>
> Paul
>
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