Subject: Re: vector bit-select in sensitivity list
From: Paul Graham (pgraham@Cadence.COM)
Date: Fri Aug 09 2002 - 07:42:05 PDT
> I don't have the LRM with me, but what I think it says
> is either that if the port declaration includes a net/var type, such as reg,
> then it may not be so redeclared, or that if the port declaration includes the
> type
> of port (e.g., output) then it may not be so redeclared.
Find me a citation.
Section 12.3.4, List of ports declarations, second paragraph, reads:
Each declared port provides the complete information about the
port. The port's direction, width, net, or variable type, and
whether the port is signed or unsigned is completely described.
The same syntax for input, inout, and output declarations is used
in the module header as would be used for the list of port style
declaration, except the list_of_port_declarations is included in
the module header rather than separately (after the ; which
terminates the module header).
Furthermore, the example in section 12.3.4 contains the comment:
// It is illegal to redeclare any ports of the module in the body
// of the module.
I take this to mean that a redeclaration like:
module m(output x);
reg x;
is illegal, and that the port must be written as:
module m(output reg x);
If it were possible to redeclare an output port as a reg within the module,
then the second sentence of the paragraph quoted above would be meaningless:
The port's direction, width, net, or variable type, and whether
the port is signed or unsigned is completely described.
I think this is pretty clear.
Paul
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