Subject: Re: vector bit-select in sensitivity list
From: Paul Graham (pgraham@Cadence.COM)
Date: Thu Aug 08 2002 - 20:13:32 PDT
Your example appears to be illegal. LRM 12.3.4 seems to say that no port
declared in a list_of_port_declarations may be redeclared in the body of the
module. Yet in your example port 'c' is redeclared in the reg declaration.
Am I misconstruing the LRM?
> module foo (
> input [7:0] a,
> input b,
> input d,
> output c);
>
> reg c;
>
> always @ (b, a[5], d)
> c = a[5] && b;
>
> endmodule
Paul
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