Subject: Re: vector bit-select in sensitivity list
From: Steve Golson (sgolson@trilobyte.com)
Date: Thu Aug 08 2002 - 18:35:26 PDT
Michael McNamara wrote:
>
> Steve Golson writes:
> > Michael McNamara wrote:
> > >
> > > To me, it is a bug in DC.
> > >
> > > As a user I really hate when a tool tells me:
> > >
> > > The construct: 'always @(a[5]) ' is not supported. Please recode
> > > this as 'wire w = a[5]; always @(w)'.
> > >
> > > As a workaround for one release, I am OK with this; but in general,
> > > as I am paying big bucks for this synthesis tool, by the next
> > > release the vendor should make the tool do this work automatically.
> >
> > It's a bug that's been in DC a long, long time. The new PRESTO Verilog
> > front-end has the same problem.
> >
> > Note that "fixing" this will not affect DC logic generation. It just affects
> > whether or not DC gives you a Warning.
>
> So, you are sating that DC does the right thing when building logic,
> but in a perfect world should just refrain from emitting the error?
Yes. DC ignores what's in the sensitivity list. It always has.
If you leave something out, it tries to be nice and give you an warning,
but it builds the logic *assuming* you meant it to be fully-specified.
> Synopsys does seem to have turned over a new leaf in their stance on
> standards these days (endorsing SystemVerilog, et cetera); perhaps we
> can get them to finally fix this issue.
Good news! In 2001.08 this is fixed. You *can* have a bit-select in
a sensitivity list.
This example:
module foo (
input [7:0] a,
input b,
input d,
output c);
reg c;
always @ (b, a[5], d)
c = a[5] && b;
endmodule
gives this
Running PRESTO HDLC
Compiling source netlist file /home/sgolson/play/foo.v
Presto compilation completed successfully.
foo
and here is the resulting netlist
module foo ( a, b, d, c );
input [7:0] a;
input b, d;
output c;
GTECH_AND2 C4 ( .A(a[5]), .B(b), .Z(c) );
endmodule
Looks good to me!
It works the same if the sensitivity list is
always @ (d or a or b)
but if you do this
always @ (d or b)
then you get a warning
Running PRESTO HDLC
Compiling source netlist file /home/sgolson/play/foo.v
Warning: /home/sgolson/play/foo.v:11: 'a[5]' is read but does not appear in the sensitivity list of this 'always' block. (ELAB-292)
Presto compilation completed successfully.
foo
but the resulting netlist is the same as above!
Note the extra 'd' in the sensitivity list is always ignored with no Warning.
-seg
Steve Golson / Trilobyte Systems / +1.978.369.9669 / sgolson@trilobyte.com
Consulting in: Verilog, Synopsys, patent analysis, reverse engineering
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