Subject: Re: vector bit-select in sensitivity list
From: Michael McNamara (mac@verisity.com)
Date: Thu Aug 08 2002 - 13:07:34 PDT
Steve Golson writes:
> Michael McNamara wrote:
> >
> > To me, it is a bug in DC.
> >
> > As a user I really hate when a tool tells me:
> >
> > The construct: 'always @(a[5]) ' is not supported. Please recode
> > this as 'wire w = a[5]; always @(w)'.
> >
> > As a workaround for one release, I am OK with this; but in general,
> > as I am paying big bucks for this synthesis tool, by the next
> > release the vendor should make the tool do this work automatically.
>
> It's a bug that's been in DC a long, long time. The new PRESTO Verilog
> front-end has the same problem.
>
> Note that "fixing" this will not affect DC logic generation. It just affects
> whether or not DC gives you a Warning.
So, you are sating that DC does the right thing when building logic,
but in a perfect world should just refrain from emitting the error?
Synopsys does seem to have turned over a new leaf in their stance on
standards these days (endorsing SystemVerilog, et cetera); perhaps we
can get them to finally fix this issue.
>
> -seg
>
> Steve Golson / Trilobyte Systems / +1.978.369.9669 / sgolson@trilobyte.com
> Consulting in: Verilog, Synopsys, patent analysis, reverse engineering
>
>
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