RE: (* synthesis, keep [=<optional_value>] *)

Subject: RE: (* synthesis, keep [=] *)
From: Muzaffer Kal (muzaffer@dspia.com)
Date: Thu Jan 31 2002 - 09:19:26 PST

hi Ben,
"Standard for VerilogŪ RTL Synthesis need not be concerned with what the
synthesis tool may or may not do."
Isn't this a contradiction ? As an example, by defining "keep" we are
telling the synthesis tool that "it may not remove this net/register" from
the design.

regards,

Muzaffer
  -----Original Message-----
  From: owner-vlog-synth@server.eda.org
[mailto:owner-vlog-synth@server.eda.org]On Behalf Of VhdlCohen@aol.com
  Sent: Thursday, January 31, 2002 8:36 AM
  To: krishna@synplicity.com
  Cc: vlog-synth@server.eda.org
  Subject: Re: (* synthesis, keep [=<optional_value>] *)

  In a message dated 1/30/02 6:35:12 PM Pacific Standard Time,
krishna@synplicity.com writes:

    <My question is if a synthesis tool needs to replicate an object
    (for better timing, or to meet fanout constraints in the FPGA world)
    that has a keep on it, should it do it be allowed to replicate the
    object ??>

  1. First reaction to question: Yes, synthesis tool may replicate the
object.
  2. Afterthoughts: Our IEEE P1364.1 Standard for VerilogŪ RTL Synthesis
need not be concerned with what the synthesis tool may or may not do. Seems
that this is a tool issue.

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  Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
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