Subject: Re: (* synthesis, keep [=
In a message dated 1/30/02 6:35:12 PM Pacific Standard Time,
1. First reaction to question: Yes, synthesis tool may replicate the object.
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: Thu Jan 31 2002 - 08:44:15 PST
From: VhdlCohen@aol.com
Date: Thu Jan 31 2002 - 08:35:55 PST
krishna@synplicity.com writes:
> <My question is if a synthesis tool needs to replicate an object
> (for better timing, or to meet fanout constraints in the FPGA world)
> that has a keep on it, should it do it be allowed to replicate the
> object ??>
2. Afterthoughts: Our IEEE P1364.1 Standard for VerilogŪ RTL Synthesis need
not be concerned with what the synthesis tool may or may not do. Seems that
this is a tool issue.
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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