I don't agree on this. In my opinion, the synthesis tool is correct in
generating an inverter with a feedback loop. I don't even believe any warning
should be displayed. Well, maybe in the extremely simple case you described, a
tool such as lint could warn the (potentially) beginner that what he coded
probably wasn't what he intended.
But there are plenty of valid designs which contain loops the way you describe
them. They are valid designs. Think in terms of false paths. Sometimes signal A
is needed to compute signal B. In another state of the design, it's the
opposite: signal B is used to compute signal A. If you look at the schematics,
you will see a loop. But the loop itself is never activated - at least if the
designer coded the whole thing right.
You can't decide that synthesis tools should reject such constructs. There are
perfectly valid.
Alain.
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