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Hi,
These are my inputs to the Feb 23, 1999 TeleConference on IEEE P1364.1 /
D1.2 (Latest revision as of Feb 12, 1999).
SECTION 4.1: Combinational Logic Verification
Section 4.1 says "A model is not compliant with this standard if it is
possible for combinational outputs to never reach a steady state."
The example: always A = #5 ~A; // Not compliant with the standard
because it exhibits oscillatory behavior.
When the above example is synthesized, Synopsys issues a warning
"Variable A is being read but does not occur in the timing control of
the block which begins there." This is because "A" is not present in the
sensitivity list and this can cause simulation mismatch with respect to
synthesis. The synthesis results in an invertor with a feedback loop. It
is also said in section 4 "Combinational logic have no storage - the
outputs are a pure function of the inputs with no internal loops." But
the synthesized result contradicts that because an internal loop is
formed between the output and input of the invertor. This is a primitive
version of a latch.
What about these combinational logic models ?
2. always @ (A) A = #5 ~A; //This has "A" in the sensitivity list. But
still produces an invertor with a feedback loop when synthesized. This
example can be added to the pre-existing one as it is not compliant with
the standard because it exhibits oscillatory behavior (This is because
of functional mismatch between the actual model and the synthesized
version).
3. always @ (A) A = ~A; //The only difference between this example and
example#1 & 2 is the omission of delay #5. Even this example results in
an invertor with a feedback loop when synthesized. This example can be
added to the pre-existing ones. But looking at the way this example is
modelled it seems to be correct. In this case probably a latch with
output being "Inverted One - NQ instead of Q" for an input of "A" which
is fed into D input of the Latch will be appropriate. "A" can also be
fed into the CLK input may be the correct synthesized version (Should
this be the from the NQ pin of the D-Latch?).
It just doesn't suffice if the tool gives a warning (Synopsys just
issues a warning only in case of example#1 and doesnot issue warnings
for example 2 & 3. I dont know what warnings are issued in Exemplar or
BuildGates).
In all these examples the synthesis results in an invertor with a
feedback loop. This is incorrect.
To summarize the synthesis tool should not let this logic develop
because of the combinatorial functionality of the above examples. The
synthesis tool should only synthesize an invertor with no feedback loop
or create an appropriate D-Latch as in case of example#3 or an
appropriate logic. Giving a warning is not sufficient.
SECTION 5.2.2.1
Another suggestion in section 5.2.2.1 (Page# 13) in the always statement
can be changed in the following lines:
always @ (posedge condA or negedge condB or ..... posedge Clock)
// .....
if (<condA>) // "positive polarity since posedge <condA>" should
be changed to "positive polarity or set since posedge <condA>"
// ......
else if (! <condB>) // "negative polarity since negedge <condB>"
should be changed to "negative polarity or reset since negedge <condB>"
else if (! <condC>)
....
....
else // Implicit posedge Clock/
// ... <synchronous logic>
This makes the asychronous set or reset correspond with postive or
negative polarity respectively and makes the comments more explicit and
clear.
SECTION 5
The final suggestion is to make the example numbering match with the
section and sub-section headings.
For example in section 5,
Example 4.1.1 in sub-section 5.1 should be numbered 5.1.1, so on and so
forth with all the sub-sections 5.2.2, 5.2.2.1, 5.3, and 5.4 in section
5.
Regards -- Subbu
PS: Is anybody from the committee joining the TeleConference in
Bay-Area. I will like to join them to participate in this
teleconference. (Ken ? or any other working committee member).
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Hi,
These are my inputs to the Feb 23, 1999 TeleConference on IEEE P1364.1 / D1.2 (Latest revision as of Feb 12, 1999).
SECTION 4.1: Combinational Logic Verification
Section 4.1 says "A model is not compliant with this standard if it is possible for combinational outputs to never reach a steady state."
The example: always A = #5 ~A; // Not compliant with the standard because it exhibits oscillatory behavior.
When the above example is synthesized, Synopsys issues a warning "Variable A is being read but does not occur in the timing control of the block which begins there." This is because "A" is not present in the sensitivity list and this can cause simulation mismatch with respect to synthesis. The synthesis results in an invertor with a feedback loop. It is also said in section 4 "Combinational logic have no storage - the outputs are a pure function of the inputs with no internal loops." But the synthesized result contradicts that because an internal loop is formed between the output and input of the invertor. This is a primitive version of a latch.
What about these combinational logic models ?
2. always @ (A) A = #5 ~A; //This has "A" in the sensitivity list. But still produces an invertor with a feedback loop when synthesized. This example can be added to the pre-existing one as it is not compliant with the standard because it exhibits oscillatory behavior (This is because of functional mismatch between the actual model and the synthesized version).
3. always @ (A) A = ~A; //The only difference between this example and example#1 & 2 is the omission of delay #5. Even this example results in an invertor with a feedback loop when synthesized. This example can be added to the pre-existing ones. But looking at the way this example is modelled it seems to be correct. In this case probably a latch with output being "Inverted One - NQ instead of Q" for an input of "A" which is fed into D input of the Latch will be appropriate. "A" can also be fed into the CLK input may be the correct synthesized version (Should this be the from the NQ pin of the D-Latch?).
It just doesn't suffice if the tool gives a warning (Synopsys just issues
a warning only in case of example#1 and doesnot issue warnings for example
2 & 3. I dont know what warnings are issued in Exemplar or BuildGates).
In all these examples the synthesis results in an invertor with a feedback
loop. This is incorrect.
To summarize the synthesis tool should not let this logic develop because of the combinatorial functionality of the above examples. The synthesis tool should only synthesize an invertor with no feedback loop or create an appropriate D-Latch as in case of example#3 or an appropriate logic. Giving a warning is not sufficient.
SECTION 5.2.2.1
Another suggestion in section 5.2.2.1 (Page# 13) in the always statement can be changed in the following lines:
always @ (posedge condA or negedge condB or ..... posedge Clock)
// .....
if (<condA>) // "positive
polarity since posedge <condA>" should be changed to "positive polarity
or set since posedge <condA>"
// ......
else if (! <condB>) // "negative polarity
since negedge <condB>" should be changed to "negative polarity or
reset since negedge <condB>"
else if (! <condC>)
....
....
else // Implicit posedge Clock/
// ...
<synchronous logic>
This makes the asychronous set or reset correspond with postive or negative polarity respectively and makes the comments more explicit and clear.
SECTION 5
The final suggestion is to make the example numbering match with the
section and sub-section headings.
For example in section 5,
Example 4.1.1 in sub-section 5.1 should be numbered 5.1.1, so on and so forth with all the sub-sections 5.2.2, 5.2.2.1, 5.3, and 5.4 in section 5.
Regards -- Subbu
PS: Is anybody from the committee joining the TeleConference in Bay-Area.
I will like to join them to participate in this teleconference. (Ken ?
or any other working committee member).
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email;internet: subbu@eng.adaptec.com
title: Design Engineer
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