As a member of the 1364 Standards group (Behavioral Task Force), I have
made the following proposal to include "attributes" in Verilog, which could
easily be used to specify pragma information to synthesis tools. The basic
premise of attributes is that they contain embedded information in the
source code which can be used to specify tool-specific information - such
as pragmas, configuration information, cycle-based information, etc - but
that does not affect the simulation behavior of the model. Synthesis
pragmas such as parallel_case and full_case are classic examples of this
type of information, and there seems to be support for coming up with a
mechanism other than comments to specify this data.
Below is the BNF for this proposal. I have spoken with Bhasker, and he has
graciously offered some time during the pragma discussion of your
conference call today for me to discuss this proposal with you. There are
essentially two related issues that need to be resolved separately:
1) What are the synthesis pragmas that need to be specified?
2) What is the syntactic mechanism for specifying them?
This proposal addresses the second question, leaving the first question for
you to decide.
Here is the proposal. Your comments and questions are welcomed.
Thanks,
-Tom
module top(b,c);
output b;
reg clk,a;
wire b,c;
// instantiate a vhdl module here:
vhdlmod vhdlmod(clk,a,b);
// instantiate a cycle-sim module here:
cyclemod (* cycle = 1; *) cyclemod(clk,a,c);
endmodule
module vhdlmod(clk,a,b) (* foreign = "VHDL WORKLIB.E:a"; *);
input clk,a;
output b;
...
endmodule
Please note that the '(* - *)' syntax was chosen because it is a lexical
token pair that is not currently used in the Verilog language.
Here's the BNF:
This is what an attribute is:
<instance_attr> ::= (* <attr_list> *)
<attr_list>::
::= <attr><,attr>*
<attr>
::= <attr_spec_list>;
<attr_spec_list>
::= <attr_spec><,attr_spec>*
<attr_spec>
::= <attr_name> = <value>
||= <attr_name>
<value>
::= <constant>
||= <constant_expression>
This is how an attribute is used:
variable instances:
<type><range>?<instance_attr><instances>+
<type>
::= REG
||= TIME
||= INTEGER
||= INPUT
||= OUTPUT
||= INOUT
REAL <instance_attr>?<instances>+
REALTIME <instance_attr>?<instances>+
EVENT <instance_attr>?<events>+
<net_type><strength>?<expandrange>?<delay>?<instance_attr>?<net_expression>;
<net_expression>
::= <net_name>
||= <net_name> = <expression>
gate and switch instances:
<gate_type> [<drive_strength>] [<delay>] [<instance_attr>]
<gate_instance>+;
module and udp declarations and instantiations:
MODULE <module_name> [<port_list>] [<instance_attr>];
[<module_item>]
ENDMODULE
PRIMITIVE <prim_name> ((port_list) [<instance_attr>];
<prim_declaration>+
[<prim_initialization>]
<table_definition>
ENDPRIMITIVE
Module or udp ports:
<port_type> [<range>] [<instance_attr>] <list_of_variables>;
<port_type> ::= INPUT
||= OUTPUT
||= INOUT
Function and Task declarations and invocations:
FUNCTION [<range>] <function_name> [<instance_attr>];
<tf_declarations>+
[<statement>]
ENDFUNCTION
TASK <task_name> [<instance_attr>] ;
<tf_declarations>+
[<statement>]
ENDTASK
built-in operators:
<unary_op> [<instance_attr>] <expression>
<expression> <binary_op> [<instance_attr>] <expression>
? [<instance_attr>] <expression> : <expression>
The BNF could be extended to include case/x/z statements as follows:
case_statement ::=
case ( expression ) [<instance_attr>] case_item { case_item } endcase
| casez ( expression ) [<instance_attr>] case_item { case_item } endcase
| casex ( expression ) [<instance_attr>] case_item { case_item } endcase
case_item ::=
expression { , expression } [<instance_attr>] : statement_or_null
| default [<instance_attr>] [ : ] statement_or_null
This would allow a case statement to look something like this:
case (state) (* parallel_case, full_case; *)
1'b0: <statement>;
1'b1: <another_statement>
endcase
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
Cycle Simulation Products 270 Billerica Rd.
Logic Design and Verification Business Unit Chelmsford, MA 01824
x6438 (978)446-6438