Attached are minutes for telecon meeting held on Feb 22.
- bhasker
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Meeting Minutes: Verilog Synthesis Interoperability Working Group
Telecon held on Feb 22, 1999
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Participants:
Ed Arthur
J. Bhasker
Cliff Cummings
Tom Fitzpatrick
Doug Smith
Jenjen Tiao
Due to funding issues, we had lost our support for an editor. This prevented
us from having a meeting in January. Bhasker is filling in this role
temporarily until we can find a more suitable replacement. If you are
interested in serving as an editor, please contact Bhasker
at jbhasker@cadence.com.
Doug Smith started off by presenting the pragmas.
RTL_synthesis on/off
RTL_full/Parallel_case
These are defined just for synthesis.
Black box and FSM could be useful but are possibly outside of synthesis tools.
May be useful. Supported by Synplicity. Black Box associated with module
instantiation and module definition - similar to don't touch.
FSM associated with a module definition.
Doug to propose these new pragmas to the reflector.
Ken's proposal to put technology-specific info was deemed outside the
scope of this document.
Technology-specific info could cause discussions to bog down.
Cliff asked - why introduce new pragma names instead of using existing ones?
These are directed specifically at RTL synthesis (as opposed to high-level synthesis, etc.).
VHDL uses the same names.
Bhasker asked - why not use `ifdef?
This would require having to recompile for synthesis
Discussion of Cadence 1364 attribute proposal.
Why not add "attribute" to the language?
Proposal is good.
What about `pragma? `endpragma? (Edward Arthur)
`parallel_case, `full_case could use
What other attributes would be proposed? Bhasker doesn't want to use 1364.1 to come up with new syntax. Will be passed on to the 1364 committee.
Cliff pointed out a problem on page 16 with assigns in procedural blocks -
will be fixed.
Compiler directives - what does "supported" mean?
Most compiler directives should be read and ignored.
The spec should state explicitly what they should do.
Define undef include else ifdef endif to be supported, the rest ignored. - doc
will be updated.
Issue was raised as to how `celldefine should be used - should it be ignored
or behave like synthesis on/off? - will be discussed seperately on the
reflector.
For `define, a clarification will be added to the doc that says that
parameterization, multiline and nested `defines shall be supported.
celldefine/endcelldefine are duplicated in doc - will be deleted.
Next we started discussion on section 5, semantics.
5.1. Addline "comb logic shall be modeled using net declaration assignment".
Change all "non-blocking" to "blocking" (no hyphen).
5.1. 4th para: Do not restrict event list to contain only variables read within
always.
5.1 4th para, last line, qualify always statement with "always statement
using blocking assignments".
(From Subbu) Correct example numbering.
4th last line, pg 11: may to might.
5.2 change to "has one or more edge events"
5.2.2. 2nd para, "shall" is too harsh. change to "should". And add comment as
to why.
Ex 4.2.2.1: add decl for OUT.
ex 4.2.2.3/4: Change wording of "may be with a synchronous reset" - it is
awkward.
Comment in Ex 4.2.2.5: Also list it as a rule in 5.2.2.
ex 4.2.2.1.3/4: change to NBA. Also change 'xFF to 8'hFF.
(From Shalom) 5.3, item 2: Change as suggested by Shalom in a previous email.
5.3 (from Shalom): Add "NBAs should be used for var that model latches. BA
may be used for var that are temp assigned and used within an always".
5.4: Add example for last stmt in first para.
Also discussed email from Subbu about the example in 4.1: conclusion was that
we should not be suuporting such constructs for synthesis as they are
meaningless in hardware.
The next working group meeting will be a face-to-face meeting at
the HDL conference in Santa Clara on April 6 evening (6 to 9pm). More
details to follow later.
Thanks to TomF for noting part of these meeting minutes.