Subject: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Wed May 30 2001 - 06:09:43 PDT
The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, JULY 06 from 12:00pm to 1:30pm
EASTERN STANDARD TIME.
Call <info will be sent later>,
and enter the passcode 007007.
Agenda:
1. To discuss the synthesizability of the following new features
of Verilog-2000:
- generate block
- multidimensional arrays
- bit and part-select with arrays
- Enhanced file i/o
(others at future meetings)
2. Looking for a leader to help out with the documentation.
Future telecon dates: Aug 10, Sept 14
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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