Subject: pragma suggestions
From: Muzaffer Kal (muzaffer@dspia.com)
Date: Sun Dec 09 2001 - 00:58:42 PST
hi,
1) one attribute for which I feel the need very frequently and which is
actually implemented in DC as a synthesis command is create_generated_clock.
I propose that we add a pragma to annotate the output of a flip-flop as a
generated clock. I suggest the syntax to be
(* synthesis, generated_clock, source = master_pin, [divide_by = number, |
multiply_by = number, ] [duty_cycle = percent, ] [edges = edge_list])
2) I also suggest that we add initialization support for RAM models too. It
would be very useful if we can find a way to pass the INIT values most FPGAs
support to both simulators and synthesizer so that a single initialization
can be used both for simulation and synthesis. I'll work to make a more
concrete proposal on this one.
Muzaffer Kal
408.654.9573 DSPIA Inc. http://www.dspia.com
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