Subject: Re: pragma suggestions
From: VhdlCohen@aol.com
Date: Mon Dec 10 2001 - 14:29:47 PST
Muzaffer,
Your reply brings a few interesting point that we must consider in our
description of ROM/RAM:
1. We need to add a note as follows:
"NOTE: There could be a simulation mismatch if during simutlation the
"initial" block is not first executed prior to the reading of the ROM (or
RAM).
Simulation must thus insure that the ROM (or RAM) is read after time
zero.
2. Synthesis will ignore initial statements, unless a variable modified
within the initial statement is qualified with a pragma. For example:
(* synthesis, rom_block = "ROM_CELL XYZ01" *)
reg [3:0] rom[0:7];
On the subject of RAM initialization, what about REGISTER initialization
also?
Perhaps we could handle register and RAM initialization, with the ''initial"
statment, just like the ROM, but the caviots discussed above.
example (untested)
module ram_2dimarray_initial(
input wire we, rd, // write enable, read
inout wire [3:0] data, // data bus
input wire [2:0] a); // address
// declares a memory rom of 8 4-bit registers.
//The indices are 0 to 7
(* synthesis, ram_block = "RAM_CELL XYZ01" *)
reg [3:0] ram[0:7];
initial $readmemb("ram.data", ram);
always @(negedge we) ram[a] <= data;
assign data = ram[a];
endmodule
In a message dated 12/10/01 12:33:53 AM Pacific Standard Time,
muzaffer@dspia.com writes:
> <In synplify the pragma (synthesis xc_props = "INIT=...") is used to
> initialize xilinx memories, IOW INIT is a xilinx specific property for
> memory initialization.
> Is it possible to use a $readmem in initial block, get it ignored by the
> synthesis tool and use an init property when the memory is inferred ? If we
> can mark the specific $readmem as a non-initializer for the memory, this
> should work. For simulation, the initial would do the initialization and
> not interfere with the memory writes. For synthesis, initial would be
> ignored and the synthesis tool would pick up the property. The ideal case
> would be if we can get a synthesis property which accepts a filename, from
> which the data would be read, in a parameter. I think a parameter would
> also be acceptable as the filename in a $readmem so this also solves the
> problem of two initialization value sets getting out of sync.>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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