Subject: RE: pragma suggestions
From: Muzaffer Kal (muzaffer@dspia.com)
Date: Mon Dec 10 2001 - 00:18:21 PST
In synplify the pragma (synthesis xc_props = "INIT=...") is used to
initialize xilinx memories, IOW INIT is a xilinx specific property for
memory initialization.
Is it possible to use a $readmem in initial block, get it ignored by the
synthesis tool and use an init property when the memory is inferred ? If we
can mark the specific $readmem as a non-initializer for the memory, this
should work. For simulation, the initial would do the initialization and not
interfere with the memory writes. For synthesis, initial would be ignored
and the synthesis tool would pick up the property. The ideal case would be
if we can get a synthesis property which accepts a filename, from which the
data would be read, in a parameter. I think a parameter would also be
acceptable as the filename in a $readmem so this also solves the problem of
two initialization value sets getting out of sync.
Muzaffer
-----Original Message-----
From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of
VhdlCohen@aol.com
Sent: Sunday, December 09, 2001 5:30 PM
To: vlog-synth@eda.org
Subject: Re: pragma suggestions
In a message dated 12/9/01 1:13:35 AM Pacific Standard Time,
muzaffer@dspia.com writes:
<
2) I also suggest that we add initialization support for RAM models too.
It
would be very useful if we can find a way to pass the INIT values most
FPGAs
support to both simulators and synthesizer so that a single
initialization
can be used both for simulation and synthesis. I'll work to make a more
concrete proposal on this one.>
I often see this request on newsgroup. Below is a recent example:
<<I needed synthesized VHDL description. Leonardo says:
"W:/vhdl/BJCards.VHD",line 457: Warning, initial value for Mem is ignored
for synthesis.
But ACEX1 EP1K50QC208 supports initializing a memory. How to explain this
for Leonardo>>
Initalizing a RAM in the INITIAL block creates a conflct in the basic
synthesis rule that a reg variable cannot be assigned values in concurrent
blocks. Int eh case of a ROM, that's not a problem since the ROM is only
assigned in the INITIAL block (see rom/ram proposal). But the in the ram
case, the ram would be assigned in both the initial and in a separate block
(at write enable).
SUggestions? I could not find anything in the Synplify documentation.
--------------------------------------------------------------------------
-- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 -------------------------------------------------------------------------- ----
This archive was generated by hypermail 2b28 : Mon Dec 10 2001 - 00:17:19 PST