Re: Assignments in the Verilog RTL Synthesizes draft

Subject: Re: Assignments in the Verilog RTL Synthesizes draft
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Sun Mar 17 2002 - 07:56:51 PST

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Hi, All -

Looks like a minor bug to fix.

Regards - Cliff

At 09:05 AM 3/13/02 +0200, Jacobi, Dan wrote:
>Mr. Cummings :
>This morning I approached you In the paper session in the HDLcon convention
>and pointed out an inconsistency in the "Draft Standard for Verilog Register
>Transfer Level Synthesis / D2.0" proposed draft for the IEEE 1364.1 standard
>(I thing that the D2.0 is the last draft published)
>
>Under sub-bullet 5.6.2 "Using two-dimensional array with data in initial
>statement" in page 13, example 22 is using an illegal continuous assignment
>in order to drive the variable "z" that is declared as a reg. following is
>the example quoted from the draft. (please see the high lighted RTL lines).
>
>Example 22:
>module rom_2dimarray_initial (
>output reg [3:0] z,
>input wire [2:0] a); // address- 8 deep memory
>// Declare a memory rom of 8 4-bit registers. The indices are 0 to 7:
>(* synthesis, rom_block = "ROM_CELL XYZ01" *) reg [3:0] rom[0:7];
>initial begin
>rom[0] = 4'b1011;
>rom[1] = 4'b0001;
>rom[2] = 4'b0011;
>rom[3] = 4'b0010;
>rom[4] = 4'b1110;
>rom[5] = 4'b0111;
>rom[6] = 4'b0101;
>rom[7] = 4'b0100;
>end
>assign z = rom[a];
>endmodule
>
>
>
>Another problem I found in the modified BNF in chapter 7 is the disability
>to parse net_lvalues (Assignment left hand side nets) due to the fact that
>the
>"net_levlaue" token reduces the "hierarchical_net_identifier" token and the
>"hierarchical_net_identifier" is struck through their for unsupported. I
>believe that the following rule :
> net_lvalue ::=
> hierarchical_net_identifier
> | hierarchical_net_identifier [ constant_expression ]{ [
>constant_expression ] }
> | hierarchical_net_identifier [ constant_expression ] { [
>constant_expression ] } [ constant_range_expression ]
> | hierarchical_net_identifier [ constant_range_expression ]
> | net_concatenation
>
>should be replaced with the following :
> net_lvalue ::=
> identifier
> | identifier [ constant_expression ] { [ constant_expression
>] }
> | identifier [ constant_expression ]
> { [ constant_expression ] } [ constant_range_expression ]
> | identifier [ constant_range_expression ]
> | net_concatenation
>
>I belive the same problem exists with left hand side variables as well and
>maybe with other uses of identifiers.
>
>Following I quated part of the BNF that show the problem:
>
>sub-bullet 7.4.1 Continuous assignments page 37
> continuous_assign ::= assign [drive_strength] [delay3]
>list_of_net_assignments ;
> list_of_net_assignments ::= net_assignment { ,net_assignment }
> net_assignment ::= net_lvalue =expression
>
>sub-bullet 7.7.3 Procedural continuous assignments page 43
> net_assignment ::= net_lvalue =expression
> net_lvalue ::=
> hierarchical_net_identifier
> | hierarchical_net_identifier [ constant_expression ]
> { [ constant_expression ] }
> | hierarchical_net_identifier [ constant_expression ]
> { [ constant_expression ] } [ constant_range_expression ]
> | hierarchical_net_identifier [ constant_range_expression ]
> | net_concatenation
>
>sub-bullet A.8.1 Concatenations pag e81
> net_concatenation ::= { net_concatenation_value
> { , net_concatenation_value } }
>
>sub-bullet A.9.3 Identifiers page 87
> hierarchical_net_identifier ::= hierarchical_identifier
>
>
>Many thanks !!!
>Danny.
>
>Dan Jacobi
>CAD Engineer
>Intel Corp.
>
>Intel Israel (74) Ltd.
>P.O. Box 1659
>Haifa 31015
>Israel
>
>Tel : +(972)-4-8655855

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