Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22

Subject: Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Mon Mar 18 2002 - 12:52:10 PST

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I am postponing the WG meeting from March 22 to April 5.

I havent yet had the time
to incorporate the latest updates. I would like to get the updated draft out before
the next WG meeting which will be on April 5 from 12:00pm to 1:30pm EST.

- bhasker

--
J. Bhasker
Cadence Design Systems 
7535 Windsor Drive, Suite A200, Allentown, PA 18195    
(610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com

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