Subject: Tri-state push thru
From: VhdlCohen@aol.com
Date: Tue Mar 19 2002 - 08:59:57 PST
After reading the <A HREF="http://www.petition-synplify.0catch.com/my_original_posting.html">My original posting</A> from comp.lang.verilog newsgroup, I
Also, some designers use internal tristates to mux signals, and then pass
I feel that the default should be "Tri-state push thru". In any case, we
On second thoughts, if synthesis results match RTL, then we don't have to
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: Tue Mar 19 2002 - 09:10:55 PST
noticed that we have not addressed the issue of tri-state push thru as
explained below from the posting:
For example in the verilog code (shown to completion if you want to try it
in your tool)
module ff_reset (q, d, clk, ldenb, en, rst);
output q; // output
input d; // data input
input clk; // clock
input rst; // reset, active hi
input ldenb; // load enable
input en; // to tristate
wire temp;
assign temp = en ? d : 1'bz;
reg q; // FF output
always @(posedge clk or posedge rst) begin
if (rst) q <= 1'b0;
else if (ldenb) q <= temp;
end
endmodule //ff_reset
The above will be implemented by some tools with tristate after the q_out
flipflop currently to match simulation. Actually, it will aslo create a FF
for the en, and that drives the tri-state gate enable. Some users (see <A HREF="http://www.petition-synplify.0catch.com">
http://www.petition-synplify.0catch.com> ) feel differently:
assign data = en ? data_in : 1'bz;
always @(posedge clk)q_out = data;
"it's evident that the tri-state buffer is described to be *before* theflop.
If I want the tri-state buffer after the flop, I'd write verilog to reflect
that. From my point of view, it is unacceptable that the tool makes a
decision like this by default. Formal verification tool vendors are going to
be happy about this, because for sure from now on every designer is going tor
un formal verification between RTL and gates to catch this kind of unorthodox
synthesis."
that signal thru a flop. They no not want this default.
Vendors can implement a switch (or a pragma?) to let the user select what he
needs.
HAVE NOT specificied in our spec the behavior of:
assign data = en ? data_in : 1'bz;
always @(posedge clk)q_out = data;
worry about it.
In any case, I wanted to address this issue for your comments.
Ben
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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