Subject: Question on ROM // Your opinion on reply
From: VhdlCohen@aol.com
Date: Sat Jul 13 2002 - 11:35:34 PDT
Question
5.6.2, pg 13
Can any variables be used in calculating memory values for a ROM? Can those
variables be used in other synthesizable constructs after that? Is there any
assumption that they obtain an initial value because of the calculation?
My answer:
Add the following to 5.6.2
Local variables can be used for the calculation of memory values. Variables
outside the scope of the initial statement shall not be allowed.
Example 25: // <-- that would mess up the numbering of the other examples.
module rom_2dimarray_initial (
output wire [3:0] z,
input wire [2:0] a); // address- 8 deep memory
// Declare a memory rom of 8 4-bit registers. The indices are 0 to 7:
(* synthesis, rom_block = "ROM_CELL XYZ01" *) reg [3:0] rom[0:7];
initial
begin : ROM_DEF
integer i;
for (i=0; i <= 255; i=i+1)
if (i<100) rom[i] = (i + 1) % 16;
else rom[i] = (i + 2) % 16;
end
assign z = rom[a];
endmodule
Rationale: Order of execution of initial statements is non-deterministic.
Allowing non-local variables would allow one ROM (e.g., ROM1 defined with
initial) to read content of another ROM or another non-initialized variable.
Like:
initial
begin : ROM_DEF
integer i;
for (i=0; i <= 255; i=i+1)
if (i<100) rom[i] = i + 1;
else rom[i] = rom2[i]* 2; // rom2 is in another initial statement
// THAT SHOULD NOT BE ALLOWED
end
Opinions?
Below is same code with earlier vlog style for compilation checks.
FYI
---
// style (for code debug only. Compiles OK
module rom(z, a);
output [3:0] z;
input [4:0] a;
reg [3:0] rom[0:7];
// integer i;
initial
begin : ROM_DEF
integer i;
for (i=0; i <= 255; i=i+1)
if (i<100) rom[i] = (i + 1) % 16;
else rom[i] = (i + 2) % 16;
end
assign z = rom[a];
endmodule
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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