Verilog RTL Synthesis: It is a standard! It is a standard! An IEEE Standard!

Subject: Verilog RTL Synthesis: It is a standard! It is a standard! An IEEE Standard!
From: Jayaram Bhasker (JBhasker@esilicon.com)
Date: Mon Dec 16 2002 - 05:12:08 PST

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All:
 
Last week, IEEE formally approved the 1364.1 as an IEEE standard. My thanks to all the working group
members who worked diligently in making this a standard.
 
- bhasker
------
J. Bhasker
Chair, Verilog Synthesis Interoperability Working Group
http://www.eda.org/vlog-synth
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)

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