Subject: Re: 1364.1 pragmas
From: David Bishop (dbishop@server.vhdl.org)
Date: Tue Sep 03 2002 - 16:40:49 PDT
-------- Original Message --------
Date: Tue, 3 Sep 2002 18:48:24 -0400 (EDT)
From: Steven Sharp <sharp@cadence.com>
Reply-To: Steven Sharp <sharp@cadence.com>
Subject: Re: 1364.1 pragmas
To: vlog-synth@server.eda.org, etf@boyd.com
>Maybe the PLI can't distinguish but it seems other tools could recognize:
>
>synthesis, <list of synthesis attributes>, coverage (different recognized
>domain thus ending synthesis domain), <list of coverage attributes>, etc
What does it do when it is scanning a list of synthesis attributes and
finds an unrecognized attribute? Does it assume that it is a misspelled
synthesis attribute or a new "domain" that it hasn't heard of? In the
first case, it will spew errors any time someone adds an attribute that
the tool-writer hadn't heard of. In the second case, it will be unable
to provide warnings about misspelled attributes, because it will assume
it is just the start of a new "domain".
If you want the tool to check your synthesis attributes for you, you will
have to give it a clear indication of which ones are synthesis attributes.
That requires marking the end of the list so it knows when to stop.
Incidentally, a synthesis attribute lint-checker would be a prime candidate
for a PLI-based tool. Even if the 1364.1 standard didn't specify any
"bracketing" attributes, or your synthesis tool didn't check your attributes,
you could build your own checker. Just put your own personal favorite
bracketing attributes around the synthesis attributes. Then write a PLI
app that scans your design and checks all attributes between your bracketing
ones against a list of legal synthesis attributes.
>I don't think "end" keywords will make much difference to the PLI. Consider:
>
>(* synthesis, fullcase=2, parallelcase, endsynthesis, fv, foo, fullcase=0,
>endfv *)
>
>I think we still only have one fullcase as far as the PLI is concerned. As
>I have stated in a couple of email messages now, I think formal
>verification tools would also read synthesis attributes and not duplicate
>them.
That is correct. As I said, the domain idea doesn't work. And that isn't
just for PLI; it goes for any implementation that complies with the standard.
The marking was just a way of doing the syntax checks you were asking for,
and it works for that.
>On the other hand, tools that bypass the PLI and just search for the
>required attributes enclosed within a set of funny braces with their
>preferred domain attribute listed first, will have no problem picking out
>the foo attribute of their choice, no matter what the Verilog simulator and
>PLI assign to the foo attribute.
Only if the tool is not IEEE Std 1364-2001 compliant. The standard specifies
the value of the attribute, period. It doesn't just specify it for a
simulator or PLI.
Steven Sharp
sharp@cadence.com
This archive was generated by hypermail 2b28 : Tue Sep 03 2002 - 16:47:39 PDT