>> So, what I am arguing for is a true pragma, that would be part of 1364
>> Verilog,
This would be REALLY great!!!!
This way parallel_case and full_case directives will then be understood
by both synthesis and simulation.
BTW, my earlier email on `ifdef was to avoid using the CONDITIONAL
COMPILATION directive "// rtl_synthesis off/on" and to use `ifdef instead.
I was not proposing to
use `ifdef for parallel_case and full_case. Your idea on handling
parallel case and full_case is terrific.
My next question is: when can we have it in 1364? (so we dont have to
worry about it in the synthesis 1364.1 std).
- bhasker
----- Begin Included Message -----
Date: Mon, 6 Jul 1998 10:59:49 -0700
From: mac@appr.silicon-sorcery.com (Michael McNamara)
Orig-From: Michael McNamara <mac@surefirev.com>
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To: jbhasker@lucent.com
Cc: vlog-synth@eda.org, mac@surefirev.com
Subject: Re: pragmas
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Reply-To: mac@surefirev.com
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jbhasker@lucent.com writes:
>
> I dont understand this. Why cant we standardize on using the `ifdef compiler
> directive instead of a pragma in a comment form such as:
>
> // rtl_synthesis off/on
>
One of the things I'd wished I'd done at Chronologic was process and
validate the // synopsys parallel_case directive at rtl simulation
(perhaps even compilation time) time.
Verilog always simulates case statements as priority decoders, and so
the 'bug' of lying to design compiler about the mutual exclusivity of
the case items is not observed until gate simulation time, which is
often too late.
My fear with
`ifdef SYNTHESIS
rtl_parallel_case
`endif
is that this design information is hidden from the tools that could be
useful here - the lint tools, simulators, and so on, that could help
the user a fair amount.
So, what I am arguing for is a true pragma, that would be part of 1364
Verilog, that would have some defined keywords, some which are really
useful only to a subset of the tools (synthesis, simulation) and
others which are globally useful.
--
/\ Michael McNamara <mac@surefirev.com>
/\// SureFire Verification Inc.
/\///\ <http://www.surefirev.com>
_\///\/ Formerly Silicon Sorcery
\//\/ Get my verilog emacs mode from
\/ <http://www.surefirev.com/verilog-mode.html>
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