Re: pragmas

Erich Marschner (erichm@Cadence.COM)
Mon, 06 Jul 1998 15:08:49 -0400

At 02:15 PM 7/6/98 -0400, Bhasker wrote:
>
>Mac:
>
>>> So, what I am arguing for is a true pragma, that would be part of 1364
>>> Verilog,
>
>This would be REALLY great!!!!
>
>This way parallel_case and full_case directives will then be understood
>by both synthesis and simulation.

Could we perhaps start using the word "verification" in place of
"simulation"? Simulation is not the only method for verifying a design -
it would be nice to keep formal verification in mind as well. In
particular, this issue of full_case and parallel_case directives, and their
(mis)use, is a big issue for formal verification, and the proposed pragma
could have a significant impact on formal verification tools.

This brings up a slightly more general issue: if we are concerned about
portability of code, do we mean portability among synthesis tools only? Or
do we mean portability among the various design and verification tools
involved in a typical flow? I see much more value in a standard that at
least attempts to address the latter.

Regards,

Erich

------------------------------------------------------------------------
F. Erich Marschner
Cadence Design Systems - Columbia MD, USA
phone: +1 410 872 4369 fax: +1 410 290 0353
email: erichm@cadence.com | erichm@ix.netcom.com