Re: pragmas

frm145 (frm145@microtec.net)
Mon, 6 Jul 1998 20:22:47 -0400

Yeah I like this pragma to preserve signal name during synthesis. This
allows the signal
to be observable from the top in gate level simulation. Is it introduced.

> // Don't collapse signal and use this signal name in place of any other
> naming option.
> // pragma signal_name preserve_signal

----------
> From: Michael McNamara <mac@surefirev.com>
> To: btf@boyd.com
> Cc: vlog-synth@eda.org
> Subject: pragmas
> Date: July 6, 1998 7:04 PM
>
>
>
> I am also on the Verilog Synthesizability group (1364.1), and
> one issue they have is trying to standardize the
>
> // synopsys parallel_case
>
> directives.
>
> They are proposing a buch of stuff, in the context that they
> can not change the language.
>
> But of course, what would be much better, is if we would
> introduce a pragma to the language, and go further and define some
> pragmas, while leaving others for vendors extentsions.
>
> I propose we introduce a new tick define, `pragma
>
> Further, we introduce a set of pragmas as follows:
>
> `pragma rtl_full_case
> Tells the system that every value is decoded.
>
> `pragma rtl_parallel_case
> Tells the system that each case_item is mutually exclusive,
> and hence a full priority decoder (if then [else if then]* )
> is not needed.
>
> `pragma rtl_translate_on
> `pragma rtl_translate_off
> Turns on and off synthesis translation. Can be used to wrap
> design verification code.
>
> I asked the list what other pragmas they wanted, and one of the
> gentlemen (Ken Coffman <kcoffman@atvideo.com>) said:
>
> other pragmas I'd like to see:
>
> // Define pin assignment.
> // Hierarchal assignment should be possible.
> // Pin assignment example 1
> // pragma signal_name pin_number nnn
>
> // Pin assignment example 2
> // pragma top_module_name1.lower_module_name2.signal_name pin_number nnn
>
> I know we can sometimes infer the following, but I'd rather command the
> hardware to synthesize a certain way.
>
> // Assign signal to clock enable if supported by hardware.
> // pragma signal_name clock_enable
>
> // Assign signal to global clock resource if supported by hardware.
> // pragma signal_name global_clock
>
> // Assign signal to global reset resource if supported by hardware.
> // pragma signal_name global_reset
>
> // Assign signal to global preset resource if supported by hardware.
> // pragma signal_name global_preset
>
> // Don't collapse signal and use this signal name in place of any other
> naming option.
> // pragma signal_name preserve_signal