>> One question from that effort, was why 1364.1 prefixes the directive
>> with rtl_? Are you leaving room for // behavioral_synthesis on ?
Yes. Different kind of tools may turn on/off certain sections of code.
For example, in FormalCheck(formal verification tool),
we have formalcheck on/off pragmas
which may or may
not match the rtl_synthesis on/off comments.
- bhasker
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From: Michael McNamara <mac@surefirev.com>
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Date: Fri, 23 Apr 1999 14:34:19 -0700 (PDT)
To: Jayaram Bhasker <jbhasker>
Cc: vlog-synth@eda.org
Subject: Compilation pragmas
X-Mailer: VM 6.43 under 20.4 "Emerald" XEmacs Lucid
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Jayaram Bhasker writes:
> Hi Folks,
>
> One of the issues discussed at the last 1364.1 WG meeting was whether a new
> construct in the upcoming version of the Verilog language (1364-1999)
> is needed to support conditional compilation, such as `rtl_synthesis on/off.
>
> The conclusion was that the two mechanisms currently available:
>
> // rtl_synthesis on/off (proposed in 1364.1)
>
> and
>
> `ifdef `fi (already in 1364-1995)
>
> are sufficient for modeling conditional compilation for synthesis purposes.
>
> If you disagree, please explain what kind of new construct you would like
> to see in the upcoming Verilog language (1364-1999) to support this.
>
> - bhasker
You are aware that Cadence is proposing adding to 1364-1999:
(* rtl_synthesis on *)
and in general, the construct-that-was-formally-known-as-attributes
for all the things that tool vendors placed in comments.
One question from that effort, was why 1364.1 prefixes the directive
with rtl_? Are you leaving room for // behavioral_synthesis on ?
--
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