Subject: Re: recursive instantiations of modules - MORE
From: Paul Graham (pgraham@Cadence.COM)
Date: Mon Mar 11 2002 - 08:13:51 PST
> Verilog 2001 supports recursive functions, but my read of the syntax is =
> that it does not support recursive modules.
The BNF by itself permits recursive module instantiations, as well as
recursive subprogram calls. (Of course the BNF by itself permits lots of
illegal things.) The remainder of the LRM text does not prohibit recursive
instantiations.
In Verilog-1995, there was no way to express a non-erroneous recursive
instantiation due to the lack of coditional elaboration (generate
statements). So it has been the experience of every Verilog designer to
date that recursive instantiation is impossible. But that is not the same
as saying that the LRM disallows it, and is certainly not the same as saying
that the LRM for an as-yet unimplemented language (Verilog-2001) disallows
it.
(One difference between Verilog and VHDL experts is that the Verilog expert
will typically say "simulator X allows it, so it must be legal", while the
VHDL expert will say "it does not appear as one of the cases in section
7.3.2.2, so it's illegal regardless of what simulator Y does".)
But in Verilog-2001 this deficiency has been remedied. The use of generate
statements and parameters allows, in principle, meaningful and non-erroneous
recursive instantiation of modules.
Paul
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