Subject: RE: vector bit-select in sensitivity list
From: Michael McNamara (mac@verisity.com)
Date: Thu Aug 08 2002 - 09:29:07 PDT
To me, it is a bug in DC.
As a user I really hate when a tool tells me:
The construct: 'always @(a[5]) ' is not supported. Please recode
this as 'wire w = a[5]; always @(w)'.
As a workaround for one release, I am OK with this; but in general,
as I am paying big bucks for this synthesis tool, by the next
release the vendor should make the tool do this work automatically.
Shalom Bresticker writes:
> [1 <text/plain; us-ascii (7bit)>]
> How do we relate to this?
>
> Shalom
>
>
> -------- Original Message --------
> Date: Tue, 06 Aug 2002 18:13:28 +0300
> From: Marc Neustadter<Marc.Neustadter@motorola.com>
> To: Shalom Bresticker<Shalom.Bresticker@motorola.com>
> References: <3D4E7EC4.42014C64@email.sps.mot.com>
> <3D4FD54F.8783D4F8@motorola.com>
>
> Shalom,
>
> DC reads it, but doesn't like it. See the attached Verilog file. I get
> the following warnings:
>
>
>
> Warning: Only simple variables are checked in the sensitivity list. The
> variable in the sensitivity list
> on line 24 will be ignored. (HDL-178)
> Warning: Variable 'vector' is being read
> in routine test line 24 in file '/users/marc/junk/test.v',
> but does not occur in the timing control of the block which
> begins
> there. (HDL-180)
>
>
>
>
> The man page for HDL-178:
>
> NAME
> HDL-178 (warning) Only simple variables are checked in
> the sensitivity list. The variable in the sensitivity
> list on line %d will be ignored.
>
>
> DESCRIPTION
> The list of variables to which a process (in VHDL) or
> an always block (in Verilog HDL) is sensitive must
> contain simple variable names. Lists that contain
> indexed variables or not-processed variables are
> ignored.
>
>
> WHAT NEXT
> If possible, rewrite the description so that the
> sensitivity list contains only simple names. As you
> rewrite the description, be careful not to introduce
> errors by making the process or block sensitive to more
> variables than necessary. The usual workaround is to
> assign to a temporary variable the required bit or
> slice of the variable, and to make the process or block
> sensitive to this temporary variable.
>
>
> EXAMPLES
> VHDL
>
> process ( bus(1) ) begin
> -- bus(1) is not a simple variable. The workaround
> follows:
>
> temp := bus(1);
> process ( temp ) begin
>
> Verilog
>
> always @ (bus[1]) begin
> /* bus[1] is not a simple variable. The workaround
> follows:
>
> temp = bus[1];
> always @ ( temp ) begin
>
>
>
>
> Since as we're talking about combinational logic, it should not be an
> error to add the full vector to the sensitivity list. (I think I did
> that in some design in the past.) However, it could cost you in
> simulation time since the always loop will be executed more times than
> necessary.
>
> If it is a vector of clocks or resets that are used in sequential always
> loops, the solution suggested above should be used.
>
> -Marc
>
>
> Shalom Bresticker wrote:
> >
> > I looked.
> > I did not find a way to do it.
> >
> > Sorry,
> > Shalom
> >
> > P.S. Please remember my question about 'always @(vector[5])'.
> >
> > Marc Neustadter wrote:
> >
> > > Shalom,
> > >
> > > Is there any way to count only the strong drivers on a net, using
> > > $countdrivers or otherwise?
> > >
> > > Thanks,
> > > -Marc
> >
> > --
> > Shalom Bresticker Shalom.Bresticker@motorola.com
> > Design & Reuse Methodology Tel: +972 9 9522268
> > Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
> > POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
> >
> > "The devil is in the details."
> [2 test.v <text/plain; us-ascii (7bit)>]
> module test (clk, reset, a, b, x);
>
> input clk;
> input reset;
> input a;
> input b;
>
> output x;
> reg x;
>
>
> reg [0:7] vector;
>
>
> always @(posedge clk or posedge reset)
> begin
> if (reset)
> vector <= 0;
> else
> vector <= vector + 1;
> end
>
>
> always @(a or b or vector[5])
> begin
> if (a)
> x = b ^ vector[5];
> end
>
> endmodule
>
>
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