Call for Papers IEEE/DATC EDP '99
-------------------------------------------------------------------
Sixth IEEE/DATC Electronic Design Processes Workshop
April 28-30, 1999
Monterey Beach Hotel, Monterey, CA
http://edp99.ece.utexas.edu
Abstracts and proposals for panels and invited speakers are due by March 1,
1999, to edp99@ece.utexas.edu
-----------------------------------------------------------------
EDP will provide a forum for a cross-section of the design community to
discuss state-of-the-art electronic design processes and CAD methodologies.
Specific goals of EDP 99 are to:
* Identify and evaluate key trends and known best practices that are
driving changes in the design process, with respect to technology and
the business model.
* Identify and evaluate the common barriers to product delivery with
respect to design processes.
* Identify and prioritize issues requiring further research in
development, deployment, and assessment of design processes and the
tools to support them.
* Review and update the "rolling roadmap" developed at earlier workshops
and disseminate findings to the design community at-large.
This 1 1/2 day workshop will include a mix of submitted presentations,
invited talks by academic professors in CAD and VLSI areas and by
engineering managers and CAD specialists from companies like Intel, Sun,
and IBM, and working group discussions.
Submissions of abstracts and suggestions for panels and invited speakers
are sought addressing both current and long term issues in all areas
related to design processes, including:
* Improving the design process
o Designer productivity
o Design turn-around time
o Design methodology repeatability and convergence
* Technology trends (deep sub-micron, high frequency)
o System level integration issues - mixed signal designs
o Managing and implementing large, dense designs
o The evolving role of the designer in very large designs
* Tool architecture and design styles
o Incremental design tool integration architectures
o Maintaining modularity of integrated incremental design tools
o Architectures for improving tool interchangeability
o Multi-source tool integration experiences
o Distributed and web-based design methodologies
o Standardization, data interchange, and interfaces for reuse of IP
* Measurement and evolution of design processes
o How to manage design process evolution
o Technology transfer for design process research
o Design process measurement techniques
o Design education, undergraduate and continuing
------------------------------------------------------------------------
Abstracts of 200-500 words in plain ASCII text should be submitted to
edp99@ece.utexas.edu by March 1, 1999. Presenters will be notified of
acceptance by March 15, 1999. It is expected that all accepted submissions
will be presented at the workshop. Full papers are not required and no
digest of papers will be published.
Workshop Dr. Naresh K. Sehgal Prof. Margarida F. Jacome
co-chairs: Design Technology, Intel University of Texas at Austin
Corp. jacome@ece.utexas.edu
naresh.k.sehgal@intel.com http://horizon.ece.utexas.edu/jacome
(408) 765-4179 (512) 471-2051
Organizing Margarida F. Jacome (U. Texas Austin)
committee: Naresh Sehgal (Intel)
David Hathaway (IBM)
Steve Grout (Sematech)