Subject: Re: problem with item 25
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Wed Sep 27 2000 - 12:59:52 PDT
Stefen:
I see the difference in the two draft LRMS that I have. D3, that I looked at
originally, says sec 2.8, third para,
explicitly states "Each attribute_instance may appear in the Verilog
description as a module_item, a statement, or as a modifier to a
particular statement".
And I see that it has been changed in draft D5. In D5, an attribute is no
longer a statement.
Alas, I thought what we had was a nice feature. Now we may
have to go back to the
way it currently exists in draft 1.4 of the rtl synthesis spec.
Ok, I will withdraw item 25.
- bhasker
> From stefen@boyd.com Wed Sep 27 15:28 EDT 2000
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> Date: Wed, 27 Sep 2000 12:27:50 -0700
> From: Stefen Boyd <stefen@boyd.com>
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> Hi Jayaram,
> Your item 25:
>
> 25. Conditional compilation attribute Yes
> (* rtl_synthesis_on *) (* rtl_synthesis_off *)
>
> What we gave you in the language is attributes for language
> elements, which doesn't lend itself to on/off directives such
> as this. You can add an attribute for a begin/end block, but
> you can't place attributes before and after that block to
> turn on/off attributes for the block. We need to rethink
> the model for synth on/off attributes.
>
> Regards,
> Stefen
>
> --------------------
> Stefen Boyd Boyd Technology, Inc.
> (408)739-BOYD
> stefen@boyd.com (408)481-9658 (fax)
>
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