Topic 1, Correlation with 1064.
Are we restricted to being a subset of the existing Verilog specification
or can we diverge from 1064 and/or influence 1064 to change? There are some
changes to 1064 being discussed with an antipated release early 1999.
Stefan suggests that we not restrict ourselves to the current wording of
1064 and has offered to act as liason with the 1064 working group. Bhasker
wants to make sure we do not put ourselves in series with 1064: should 1064
lag, we will continue to work on and release 1064.1.
Note: One change to 1064 is that parameters will not have width definition.
Conclusions: We will not be restricted by 1064. We will attempt to
correlate suggested changes with 1064.
Topic 2, Pragmas.
Shall we work with the existing `ifdef `else structure for language
enhancements, or shall we add comment pragmas (like // rtl_translate_off),
or shall we add language elements like `rtl_translate on/off. Note: the
primary use of this particular directive is to exlude behavioral code from
synthesis.
Conclusion: Add 'directives to the language. Directives like 'parallel_case
will appear on the line following the case statement. Other directives
include `map_to_mux, `full_case, and others. Note: There is some still
discusion on this topic. Douglas Smith is task leader for the Pragma section.
General Note: Verilog should allow direct implementation and manipulation
of hardware features. Each place where a hardware feature is available and
Verilog makes it hard to access is a source of frustration for the
designer. Example: dedicated low-skew clock enable network.
Topic 3, Syntax.
Note: 'map_to_mux is not a hard restriction, but instructs compiler to try
to implement with mux from library first and try not to create a huge slow
array of combinational logic. Apu wonders if we're opening the door to a
wide variety of compiler directives, like defining adder types (carry
look-ahead, conditional sum, etc).
Conclusion: Yes, we are.
Topic 4, Semantics.
Do global replacement of 'signals' with 'variables', of 'event' with
'sensitivity' or 'event sensitivity'.
Make sure rules do not appear embedded in examples.
Add example numbers for all examples.
4.2.2.1: show how async set/reset can be synthesized.
Review and incorporate clarifications/changes suggested by Alain Reynaud,
Shalom Bresticker, and Sudhir Kadkade.
Our format should match 1076.6 proposal as much as possible (found at
www.eda.org/siwg).