Subject: RE: 1364.1 pragmas
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Sep 20 2002 - 10:13:54 PDT
Bhasker and I talked on the phone about this yesterday.
We actually like the idea of keeping synthesis. We know that it does not
create an actual Verilog-2001 domain, but the added attribute will be nice
for synthesis. We further proposed to make the "land-grab" so that the
attributes would belong to IEEE synthesis
At 09:21 AM 9/6/02 -0700, Stefen Boyd wrote:
>Precedence: bulk
>
>At 07:23 AM 9/6/2002 -0700, Jayaram Bhasker wrote:
>>Option 1: Keep the attribute pragmas as currently described in 1364.1 draft
>>since it does not violate
>>the description of attributes as described in the 1364 standard. The issue
>>Steve brought up about
>>1364, Sec 2.8, para 4, can easily be resolved by constraining the usage of
>>attributes in 1364.1 by adding the
>>following statement to the 1364.1 draft:
>>
>>"It shall be an error to redefine these attributes for the same language
>>element. In addition, these
>>attributes shall not be overloaded to mean something else and shall not be
>>used in any other context other
>>than the way they are defined in this standard."
>
>Option 1 suggests the removal of requiring the "synthesis"
>attribute... Keeping "synthesis" suggests that we are creating
>a domain (which is what we thought we were doing). Since it
>doesn't, this could lead to confusion.
>
>Your note says that we are making the first land grab and
>everyone else had better get outa da way (or did I misread
>the intent?). Removal of the "synthesis" attribute would
>make it crystal clear what you mean by the added statement.
>
>Regards,
> Stefen
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
This archive was generated by hypermail 2b28 : Fri Sep 20 2002 - 10:33:06 PDT