Subject: Re: Inferring RAMs in Verilog
From: VhdlCohen@aol.com
Date: Sat Jul 07 2001 - 15:51:26 PDT
This might be a method to infer rams implemented with latches. Synthesizers
may yield lots of warnings though, Hopefullly, if the compiler recognizes
the attribute, it would not produce tons of warning messages.
//Ram implemented with latches
module ramlatch (q, a, d, we);
output [7:0] q; // output
input [7:0] d; // data input
input [6:0] a; // address
input we; // clock and write enable
reg [7:0] mem [127:0] /* syn_ramstyle = block_ram */;
// memory 128 deep, 8 wide
always @(/*AUTOSENSE*/a or d or we) begin
if(we)
mem[a] <= d;
end
assign q = mem[a];
endmodule
// Synchronous Ram
> module ram_test(q, a, d, we, clk);
> output [7:0] q;
> input [7:0] d;
> input [6:0] a;
> input clk, we;
> reg [7:0] mem [127:0] /* syn_ramstyle = block_ram */;
> always @(posedge clk) begin
> if(we)
> mem[a] <= d;
> end
>
> assign q = mem[a];
> endmodule
>
>
> Attribute.The syn_ramstyle attribute specifies the implementation to use
> for
> an inferred RAM. To turn off RAM inferencing, set the attribute to
> registers.
> You can apply syn_ramstyle to either a register signal driven by the RAM or
> the instance name of the RAM.
> example:
>
> reg [7:0] dataout[31:0] /* syn_ramstyle="registers" */;
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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