Subject: Re: Inferring RAMs in Verilog
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Fri Jul 06 2001 - 06:49:49 PDT
Ben:
Same for this one.
- bhasker
> From: VhdlCohen@aol.com
> Date: Sat, 23 Jun 2001 15:06:17 EDT
> Subject: Re: Inferring RAMs in Verilog
> To: vlog-synth@eda.org
> MIME-Version: 1.0
> X-Received: By mailgate.Cadence.COM as MAA28349 at Sat Jun 23 12:46:46 2001
>
> ref: IEEE P1364.1 / D1.6, Draft Standard for Verilog® Register Transfer Level
> Synthesis
> The document DOES NOT specify HOW RAMs are inferred, and which attributes if
> any can be used to infer RAMs or registers insteads of RAMs.
> Below is information from Synplify help file that addresses this issue. I
> recommend that we add a recommendation and possibly attributes to infer RAMs
> or registers.
> ----
> Synplify can infer synchronous RAMs from your Verilog source code and, where
> appropriate, generate technology-specific single or dual-port RAMs. No
> special input such as attributes or directives in your source code is needed.
> The Synplify primitive generated for an inferred RAM has an asynchronous
> READ, except as noted in Synchronous READ RAMs.
> The following is the list of supported technology-specific RAMs that Synplify
> can generate.
>
> Technology
> Vendor Family RAM Type
> Altera FLEX10K/10KE single port
> Altera APEX20K/20KE single and dual port
> Atmel 40K single and dual port
> Lucent ORCA FPSC ORCA Series 2, 3 single and dual port
> Xilinx Spartan, Spartan2, Spartan-XL
> Virtex, Virtex-E
> XC3000
> XC4000/E/EX/XL/XLA/XV
> XC5200, XC9500/XL single and dual port
> Example
>
> module ram_test(q, a, d, we, clk);
> output [7:0] q;
> input [7:0] d;
> input [6:0] a;
> input clk, we;
> reg [7:0] mem [127:0];
> always @(posedge clk) begin
> if(we)
> mem[a] <= d;
> end
>
> assign q = mem[a];
> endmodule
>
> --
> Attribute.The syn_ramstyle attribute specifies the implementation to use for
> an inferred RAM. To turn off RAM inferencing, set the attribute to registers.
> You can apply syn_ramstyle to either a register signal driven by the RAM or
> the instance name of the RAM.
>
> ere is an example:
>
> module ram4 (datain,dataout,clk);
> output dataout[31:0];
> input clk;
> input datain[31:0];
> reg [7:0] dataout[31:0] /* synthesis syn_ramstyle="registers" */;
> /* Other coding */
> ------------------------------------------------------------------------------
>
> --------------------------------------
> Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
> http://www.vhdlcohen.com/ vhdlcohen@aol.com
> Author of following textbooks:
> * Component Design by Example ... a Step-by-Step Process Using
> VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------
>
> --------------------------------------
J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com
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