Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: J. Bhasker (jbhasker@cadence.com)
Date: Thu Jan 10 2002 - 13:52:59 PST
REMINDER! REMINDER! REMINDER!
------Original Message-----
From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On
Behalf Of J. Bhasker
Sent: Tuesday, January 08, 2002 9:19 AM
To: vlog-synth@eda.org
Subject: Verilog Synthesis Interoperability Working Group Meeting:
Agenda for Jan 11, '02
The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, JANUARY 11 from 12:00pm to
1:30pm EASTERN STANDARD TIME.
Call:
USA Toll Free Number: 888-469-0503
USA Toll Number: +1-312-470-7002
PASSCODE: 57607
LEADER: Mr Jayaram Bhasker
Agenda:
1. To discuss new synthesis attributes as per action items of last meeting.
(BenC, PaulG and CliffC).
2. TO ALL: please review draft 1.8 and be prepared to present any comments.
Future telecon dates: Feb 8, 2002.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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