Subject: Re: New proposal for ROM definitions in functions and tasks
From: VhdlCohen@aol.com
Date: Wed Nov 21 2001 - 10:09:30 PST
In a message dated 11/21/01 7:44:32 AM Pacific Standard Time,
VhdlCohen@aol.com writes:
> Should we also show the examples a la Verilog-95 and a la verilog-2001 ANSI
> C Style. This question applies to ALL the examples in the new spec.
>
Question also relates to the location attributes. Thus:
// a la verilog-2001
module rom_case(
(* synthesis, rom_block = "ROM_CELLXYZ01" *)
output reg [3:0] z,
input wire [2:0] a); // address- 8 deep memory
always@* begin // @(a)
case (a)
3'b000: z = 4'b1011;
3'b001: z = 4'b0001;
3'b100: z = 4'b0011;
3'b110: z = 4'b0010;
3'b111: z = 4'b1110;
default: z =4'b0000;
endcase
end
endmodule // rom_case
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<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
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0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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