Subject: Re: New proposal for ROM definitions in functions and tasks
From: VhdlCohen@aol.com
Date: Wed Nov 21 2001 - 07:09:27 PST
Cliff,
Thanks for making teh corrections.
Should we also show the examples a la Verilog-95 and a la verilog-2001 ANSI C
Style. This question applies to ALL the examples in the new spec.
Thus, the rom 2-d would look like this:
// a la Verilog-2001 ANSI C style
module rom_2dimarray_inital (
output wire [3:0] z,
input wire [2:0] a);
(* synthesis, rom_block = "ROM_CELL XYZ01" *) reg [3:0]
rom[0:7]; // declares a memory rom of 8 4-bitregisters. The indices are 0
to 7
initial begin
rom[0] = 4'b1011;
rom[1] = 4'b0001;
rom[2] = 4'b0011;
rom[3] = 4'b0010;
rom[4] = 4'b1110;
rom[5] = 4'b0111;
rom[6] = 4'b0101;
rom[7] = 4'b0100;
end
assign z = rom[a]; endmodule
// a la verilog-95
module rom_2dimarray_inital (z, a);
output [3:0] z;
input [2:0] a;
(* synthesis, rom_block = "ROM_CELL XYZ01" *) reg [3:0]
rom[0:7]; // declares a memory rom of 8 4-bitregisters. The indices are 0
to 7
initial begin
rom[0] = 4'b1011;
rom[1] = 4'b0001;
rom[2] = 4'b0011;
rom[3] = 4'b0010;
rom[4] = 4'b1110;
rom[5] = 4'b0111;
rom[6] = 4'b0101;
rom[7] = 4'b0100;
end
assign z = rom[a]; endmodule
In a message dated 11/20/01 5:33:00 PM Pacific Standard Time,
cliffc@sunburst-design.com writes:
> Attached are two documents. The first is Ben's word file with my markups
> and notes. The second is a pdf version of the file with all changes
> implemented (it is sometimes easier to understand the markup changes if you
> can see the final product).
>
> Ben has done a nice job of assembling relevant examples. I think we still
> need more explanation surrounding, introducing and explaining the examples.
> I prettied-up the Verilog code per typical formatting that one would find
> from experienced Verilog engineers. We still need to do more formatting
> related to boxing some of the examples and fixing the boxes on others.
>
> Regards - Cliff
>
-----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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