Subject: Floating point synthesis, call for participation
From: David Bishop (dbishop@server.vhdl.org)
Date: Fri Apr 12 2002 - 19:53:37 PDT
Call for participation
We are starting a study group to look into a definition for
floating point (and possibly fixed point) synthesis packages
for both VHDL and Verilog.
Our goal is a synthesizable package, which will work the same
in both VHDL and Verilog. This will be part of an IEEE
specification.
Please look at:
http://www.eda.org/fphdl/
-- NAME: David W. Bishop INTERNET: dbishop@vhdl.org
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