Re: LRM 5.x: Unclear about when block refires on same event that changed


Subject: Re: LRM 5.x: Unclear about when block refires on same event that changed
From: VhdlCohen@aol.com
Date: Tue Feb 13 2001 - 12:41:18 PST


In a message dated 2/13/01 11:51:19 AM Pacific Standard Time,
eagle64@email.msn.com writes:
<<> The "always" behavior in your example parks for 10 time steps, then
> complements a, but notice that the event control expression cannot see this
> because the activity is located at the statement where the complement is
> taking place. Control does not return to the event control expression
> until all of the sequential statements in the behaviror have completed
> execution. When the event control expression is finally awake, it does not
> see what happened in the past.>>
>

OK, so WHERE in the LRM does it say that "Control does not return to the
event control expression until all of the sequential statements in the
behaviror have completed execution"?

Section 5.4 shows the Verilog simulation reference model
It states:
while (there are events) {
 if (no active events) {
  ...
     }
 }
 E = any active event;
 if (E is an update event) {
      update the modified object;
      add evaluation events for sensitive processes to event queue;
  } else { /* shall be an evaluation event */
  evaluate the process;
  add update events to the event queue;
 }
}

Also, in 5.6.3 Blocking assignment states "When the process is returned (or
if it returns immediately if no delay is specified), the process performs the
assign-ment to the left-hand side and enables any events based upon the
update of the left-hand side.

From the above two statements, it would seem that at time 10, "a" becomes an
updated event.
Where am I wrong?

always(@ a or @ b) // P1 block
     begin
     #10 a =~ a;
      c = b;
      end

------------------------------------------------------------------------------

--------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

--------------------------------------



This archive was generated by hypermail 2b28 : Tue Feb 13 2001 - 12:46:20 PST